This invention relates to a method of manufacturing semiconductor devices, in which the junction formation is improved.
Recently, various technical developments have been made in connection with the process of manufacturing semiconductor devices such as the oxide isolation, shallow junction formation and multilayer interconnection for the purposes of increasing the speed of operation and density of integration of the semiconductor devices. Particularly, the shallow junction formation permits extreme improvements of properties of the semiconductor device since it reduces the junction area, junction capacitance and series resistance in the device.
However, where a shallow junction is formed, the lateral diffusion length is short, so that in case when forming, for instance, an emitter region in a base region of a bipolar transistor, in the step of forming a contact hole by etching the diffusion hole it is likely that not only the emitter region but also the base region is exposed due to the etching of the side wall of the hole and hence to the increase of the hole diameter. In this case, the problem of the short-circuit of the emitter-base junction by an electrode formed on the wafer arises.
In order to solve such a problem, a method of producing a bipolar transistor as shown in FIG. 1 has been proposed. In this method, a silicon oxide layer 3 is formed on an n-type epitaxial layer 2, in which a p-type base region 1 is formed, and a diffusion hole 4 is formed in this silicon oxide layer 3. Then, a poly-silicon layer 5 doped with a great quantity of an impurity of the opposite conductivity type to the base region 1 (for instance arsenic) is formed on the entire surface, and then an n.sup.+ -type emitter region 6 is formed through thermal diffusion in the base region 1. Subsequently, the poly-silicon layer 5 is selectively removed to leave a region greater than the hole 4, and then an emitter electrode 7 is formed. By this method a poly-silicon layer portion greater than the diffusion hole 4 remains, so that emitter-base junction is not exposed and the short-circuit between the base region 1 and emitter region 6 does not occur. However, this method requires photolithography for selectively leaving a poly-silicon layer portion. In addition, a shift of the collector-base junction as shown by a broken line in FIG. 1 is caused by a high temperature thermal treatment in a diffusion furnace, so that it is difficult to control the base width.
There has also been proposed a method of manufacture of a bipolar transistor as shown in FIG. 2. In this method, after the formation of a silicon oxide layer 3 on an n-type epitaxial layer 2 having a p-type base region 1 formed therein, an opening 8 is formed in this silicon oxide layer 3, and an emitter region 9 is formed by selectively growing a single-crystalline silicon layer containing a great quantity of an emitter impurity in the opening 8, followed by the formation of an emitter electrode. This method requires no photolithography, and also by this method the emitter-base junction will not be contiguous to the emitter electrode. However, the highly advanced techniques of the selective vapor growth method are required, and also an increased number of steps are involved in the manufacturing process, thus leading to a high cost. Further, a shift of the collector-base junction as shown by a broken line in FIG. 2 is caused again by a high temperature thermal treatment in the vapor growth step like the method of FIG. 1, thus making the base width control difficult.